Execute Image Processing by using FPGA Acceleration

Authors

  • Basil N. Alhamadani Department of Electrical and Computer Engineering, Altinbas University, Istanbul, Turkey Author
  • Almanthor Motaz.M Department of Electrical and Computer Engineering, Altinbas University, Istanbul, Turkey Author

Abstract

The domain specific language for Image Processing of has made a lot of  interest taking into account its capacity of decoupling figuring from plans that  license engineers to check for cutting edge mappings concentrating on CPU  and GPU. While the Halide social order has been growing rapidly, there is at   present no genuine method to easily outline the enormous number of Halide 
tasks to powerful FPGA enlivening specialists. To deal with this test, we  propose Hetero Halide, a through and through structure for fusing Halide  undertakings to FPGA enlivening specialists. This system uses both estimation  and arranging information decided in a Halide program. Appeared differently  concerning the present strategies, stream gave by Hetero Halide is unraveled, 
as it just requires moderate changes for Halide programs on the arranging part  to be fitting to FPGAs. For part of the amassing stream, and to go about as the  midway depiction of Hetero Halide, we pick Hetero CL, a heterogeneous 
programming establishment which supports diverse use back ends, for  instance, systolic displays and stencil executions. By using Hetero CL, Hetero  Halide can create capable animating operators by picking unmistakable  backbends as demonstrated by the application. The introduction appraisal  differentiates the stimulating operator made by HeteroHalide and multi-focus 
CPU and a present Halide-HLS compiler

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Published

2021-02-01